EP1SGX10C Datasheet, PDF (172/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Table 45 shows the possible settings for the I/O standards with drive
strength control.
Table 45. Programmable Drive Strength
I/O Standard
3.3-V LVTTL
3.3-V LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
GTL/GTL+
1.5-V HSTL class I and II
1.8-V HSTL class I and II
SSTL-3 class I and II
SSTL-2 class I and II
SSTL-18 class I and II
I_OH / I_OL Current Strength Setting (mA)
24 (1), 16, 12, 8, 4
24 (2), 12 (1), 8, 4, 2
16 (1), 12, 8, 2
12 (1), 8, 2
8 (1), 4, 2
Support maximum and minimum strength
Notes to Table 45:
(1) This is the Quartus II software default current setting.
(2) I/O banks 1 and 2 do not support this setting.
The Quartus II software, beginning with version 4.2, will report current
strength as “PCI Compliant” for 3.3-V PCI, 3.3-V PCI-X 1.0, and Compact
PCI I/O standards.
Stratix GX devices support series on-chip termination (OCT) using
programmable drive strength. For more information, contact your Altera
Support Representative.
Open-Drain Output
Stratix GX devices provide an optional open-drain (equivalent to an
open-collector) output for each I/O pin. This open-drain output enables
the device to provide system-level control signals (that is, interrupt and
write-enable signals) that can be asserted by any of several devices.
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Preliminary
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