EP1SGX10C Datasheet, PDF (206/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Table 73. 3.3-V PCML Specifications
Symbol
V_CCIO
V_ID
V_ICM
V_OD
∆V_OD
V_{O C M}
∆V_{O C M}
V_T
R₁
R₂
Parameter
I/O supply voltage
Input differential voltage
swing (single-ended)
Input common mode
voltage
Output differential voltage
(single-ended)
Change in V_{O D} between
high and low
Output common mode
voltage
Change in V_{O C M} between
high and low
Output termination voltage
Output external pull-up
resistors
Output external pull-up
resistors
Conditions
Minimum
3.135
300
Typical
3.3
Maximum
3.465
600
Units
V
mV
1.5
3.465
V
300
370
500
mV
50
mV
2.5
2.85
3.3
V
50
mV
V_{C C I O}
V
45
50
55
W
45
50
55
W
Table 74. LVPECL Specifications
Symbol
V_CCIO
V_ID
V_ICM
V_OD
V_{O C M}
R_L
Parameter
Conditions
I/O supply voltage
Input differential voltage
swing (single-ended)
Input common mode
voltage
Differential output voltage
Output common mode
voltage
Receiver differential input
resistor, external
R_L = 100 Ω
R_L = 100 Ω
Minimum
3.135
300
Typical
3.3
Maximum
3.465
1,000
Units
V
mV
1
2
V
525
700
970
mV
1.5
1.7
1.9
mV
90
100
110
W
206
Preliminary
Altera Corporation