EP1SGX10C Datasheet, PDF (201/262 Pages) Altera Corporation – StratixGX FPGA Family

Operating Conditions
Table 66. Stratix GX Transceiver Block AC Specification (Part 3 of 3)
-6 Commercial &
-7 Commercial &
-5 Commercial
Industrial Speed
Industrial Speed
Symbol /
Description
Conditions
Speed Grade (5)
Grade
(5)
Grade
Unit
(5)
Min Typ Max Min Typ Max Min Typ Max
Jitter transfer Low
3
3
bandwidth (6) bandwidth
setting @
3.125 Gbps
High
4.7
4.7
bandwidth
setting @
3.125 Gbps
Low
3.2
3.2
bandwidth
setting @
2.5 Gbps
High
4.3
4.3
bandwidth
setting @
2.5 Gbps
Output t_{R I S E} 20%–80%
60
130 60
130 60
Output t_{FA L L} 20%–80%
60
130 60
130 60
Transmit
Single width 3
latency (3)
8
3
8
3
Double width 3
7
3
7
3
Intra
differential
pair skew
Channel to Within a
channel skew single
quadrant
Output return 100 MHz–2.5 –10
loss
GHz
10
50
–10
10
50
–10
N/A
MHz
N/A
MHz
3.2
MHz
4.3
MHz
130
ps
130
ps
8 Number
of parallel
clocks
7 Number
of parallel
clocks
10
ps
50
ps
dB
Notes to Table 66:
(1) UI = Unit Interval.
(2) Receive latency delay from serial receiver indata to parallel receiver data.
(3) Transmitter latency delay from parallel transceiver data to serial transceiver out data.
(4) Per IEEE Standard 802.3ae @ 3.125 for –5 and –6.
(5) All numbers for the -6 and -7 speed grades are for both commercial and industrial unless specified otherwise in
the Conditions column. Speed grade -5 is available only for commercial specifications.
(6) The numbers are for 3.125-Gbps data rate for –5 and –6 devices and 2.5 Gbps for –7 devices.
(7) The specification is for channel aligner tolerance.
Altera Corporation
201
Preliminary