EP1SGX10C Datasheet, PDF (81/262 Pages) Altera Corporation – StratixGX FPGA Family

TriMatrix Memory
non-simultaneous reads and writes, but the q[] port will output the data
once it has been written to the memory (if the outputs are not registered)
or after the next rising edge of the clock (if the outputs are registered). For
more information, see the chapter TriMatrix Embedded Memory Blocks in
Stratix & Stratix GX Devices of the Stratix Device Handbook, Volume 2.
Figure 56 shows these different RAM memory port configurations for
TriMatrix memory.
Figure 56. Simple Dual-Port & Single-Port Memory Configurations
Simple Dual-Port Memory
data[ ]
wraddress[ ]
wren
inclock
inclocken
inaclr
rdaddress[ ]
rden
q[ ]
outclock
outclocken
outaclr
Altera Corporation
Single-Port Memory (1)
data[ ]
address[ ]
wren
inclock
inclocken
inaclr
q[ ]
outclock
outclocken
outaclr
Note to Figure 56:
(1) Two single-port memory blocks can be implemented in a single M4K block as long
as each of the two independent block sizes is equal to or less than half of the M4K
block size.
The memory blocks also enable mixed-width data ports for reading and
writing to the RAM ports in dual-port RAM configuration. For example,
the memory block can be written in ×1 mode at port A and read out in ×16
mode from port B.
TriMatrix memory architecture can implement pipelined RAM by
registering both the input and output signals to the RAM block. All
TriMatrix memory block inputs are registered providing synchronous
write cycles. In synchronous operation, the memory block generates its
own self-timed strobe write enable (WREN) signal derived from the global
or regional clock. In contrast, a circuit using asynchronous RAM must
81
Preliminary