EP1SGX10C Datasheet, PDF (185/262 Pages) Altera Corporation – StratixGX FPGA Family

IEEE Std. 1149.1 (JTAG) Boundary-Scan Support
Table 56. 32-Bit Stratix GX Device IDCODE (Part 2 of 2)
Device
Version (4 Bits)
EP1SGX40
0000
IDCODE (32 Bits) (1)
Part Number (16 Bits)
Manufacturer Identity
(11 Bits)
0010 0000 0100 0101
000 0110 1110
LSB (1 Bit) (2)
1
Notes to Table 56:
(1) The most significant bit (MSB) is at the left end of the string.
(2) The IDCODE’s least significant bit (LSB) is always 1.
Figure 116 shows the timing requirements for the JTAG signals.
Figure 116. Stratix GX JTAG Waveforms
TMS
TDI
TCK
TDO
Signal
to Be
Captured
Signal
to Be
Driven
t _JCP
t _JCH
t _JCL
t _JPSU
t_JPZX
t_JSSU
t_JPCO
t_JSH
t_JSZX
t_JSCO
t _JPH
t _JPXZ
t_JSXZ
Table 57 shows the JTAG timing parameters and values for Stratix GX
devices.
Table 57. Stratix GX JTAG Timing Parameters & Values (Part 1 of 2)
Symbol
Parameter
t_{J C P}
t_{J C H}
t_{J C L}
t_{J P S U}
TCK clock period
TCK clock high time
TCK clock low time
JTAG port setup time
Min (ns) Max (ns)
100
50
50
20
Altera Corporation
185
Preliminary