EP1SGX10C Datasheet, PDF (17/262 Pages) Altera Corporation – StratixGX FPGA Family

Figure 8. Output Buffer
Serializer
Output Buffer
Programmable
Output
Driver
Transceiver Blocks
Programmable
Pre-Emphasis
Programmable
Termination
Output
Pins
Programmable Output Driver
The programmable output driver can be set to drive out 400 to 1,600 mV.
Table 9 shows the available settings for each termination value. The V_OD
can be dynamically or statically set. The output driver requires either
internal or external termination at the source.
Table 9. Programmable V_OD (Differential) Note (1)
Termination Setting (Ω)
100
120
150
V_{O D} Setting (mV)
400, 800, 1000, 1200, 1400, 1600
480, 960, 1200, 1440
600, 1200, 1500
Note to Table 9:
(1) V_OD differential is measured as V_A – V_B (see Figure 9).
Altera Corporation
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Preliminary