EP1SGX10C Datasheet, PDF (178/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Table 49 shows I/O standard support for each I/O bank.
Table 49. I/O Support by Bank (Part 1 of 2)
I/O Standard
LVTTL
LVCMOS
2.5 V
1.8 V
1.5 V
3.3-V PCI
3.3-V PCI-X 1.0
LVPECL
3.3-V PCML
LVDS
HyperTransport technology
Differential HSTL (clock
inputs)
Differential HSTL (clock
outputs)
Differential SSTL (clock
outputs)
3.3-V GTL
3.3-V GTL+
1.5-V HSTL class I
1.5-V HSTL class II
1.8-V HSTL class I
1.8-V HSTL class II
SSTL-18 class I
SSTL-18 class II
SSTL-2 class I
SSTL-2 class II
SSTL-3 class I
Top & Bottom Banks
(3, 4, 7 & 8)
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Left Banks
(1 & 2)
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Enhanced PLL External
Clock Output Banks
(9, 10, 11 & 12)
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
178
Preliminary
Altera Corporation