EP1SGX10C Datasheet, PDF (218/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Table 97. DSP Block Internal Timing Microparameter Descriptions
Symbol
t_SU
t_H
t_CO
t_INREG2PIPE9
t_INREG2PIPE18
t_{PIPE2OUTREG2ADD}
t_{PIPE2OUTREG4ADD}
t_PD9
t_PD18
t_PD36
t_CLR
t_CLKHL
Parameter
Input, pipeline, and output register setup time before clock
Input, pipeline, and output register hold time after clock
Input, pipeline, and output register clock-to-output delay
Input register to DSP block pipeline register in 9 × 9-bit mode
Input register to DSP block pipeline register in 18 × 18-bit
mode
DSP block pipeline register to output register delay in two-
multipliers adder mode
DSP Block Pipeline Register to output register delay in four-
multipliers adder mode
Combinational input to output delay for 9 × 9-bit mode
Combinational input to output delay for 18 × 18-bit mode
Combinational input to output delay for 36 × 36-bit mode
Minimum clear pulse width
Minimum clock high or low time
Table 98. M512 Block Internal Timing Microparameter Descriptions
Symbol
t_M512RC
t_M512WC
t_M512WERESU
t_M512WEREH
t_M512DATASU
t_M512DATAH
t_M512WADDRSU
t_M512WADDRH
t_M512RADDRSU
t_M512RADDRH
t_M512DATACO1
t_M512DATACO2
t_M512CLKHL
t_M512CLR
Parameter
Synchronous read cycle time
Synchronous write cycle time
Write or read enable setup time before clock
Write or read enable hold time after clock
Data setup time before clock
Data hold time after clock
Write address setup time before clock
Write address hold time after clock
Read address setup time before clock
Read address hold time after clock
Clock-to-output delay when using output registers
Clock-to-output delay without output registers
Minimum clock high or low time
Minimum clear pulse width
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Preliminary
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