EP1SGX10C Datasheet, PDF (213/262 Pages) Altera Corporation – StratixGX FPGA Family

Power Consumption
Table 91. CTT I/O Specifications (Part 2 of 2)
Symbol
V_OH
V_OL
I_O
Parameter
High-level output voltage
Low-level output voltage
Output leakage current
(when output is high Z)
Conditions
I_OH = –8 mA
I_OL = 8 mA
GND ≤ V_{O U T} ≤
V_{C C I O}
Minimum
V_{R E F} + 0.4
–10
Typical Maximum
V_{R E F} – 0.4
10
Units
V
V
µA
Table 92. Bus Hold Parameters
Parameter Conditions
1.5 V
V_{C C I O} Level
1.8 V
2.5 V
Min Max Min Max Min Max
Low sustaining V_IN > V_IL
25
30
50
current
(maximum)
High sustaining V_IN < V_IH
–25
–30
–50
current
(minimum)
Low overdrive 0 V < V_IN <
160
200
300
current
V_CCIO
High overdrive 0 V < V_IN <
current
V_CCIO
–160
–200
–300
Bus-hold trip
point
0.5
1.0 0.68 1.07 0.7
1.7
Notes to Tables 73 through 92:
(1) Drive strength is programmable according to values in Table 45 on page 172.
(2) V_{R E F} specifies the center point of the switching range.
3.3 V
Units
Min Max
70
µA
–70
µA
500 µA
–500 µA
0.8
2.0
V
Power
Consumption
Detailed power consumption information for Stratix GX devices will be
released when available.
Timing Model
The DirectDrive technology and MultiTrack interconnect ensure
predictable performance, accurate simulation, and accurate timing
analysis across all Stratix GX device densities and speed grades. This
section describes and specifies the performance, internal, external, and
PLL timing specifications.
All specifications are representative of worst-case supply voltage and
junction temperature conditions.
Altera Corporation
213
Preliminary