EP1SGX10C Datasheet, PDF (118/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Figure 77. Adder/Output Blocks Note (1)
accum_sload0 (2)
Result A
Accumulator Feedback
addnsub1 (2)
Result B
signa (2)
signb (2)
Result C
addnsub3 (2)
Adder/
Subtractor/
Accumulator1
Summation
Adder/
Subtractor/
Accumulator2
overflow0
Output Selection
Multiplexer
Output
Register Block
overflow1
Result D
accum_sload1 (2)
Accumulator Feedback
Notes to Figure 77:
(1) Adder/output block shown in Figure 77 is in 18 × 18-bit mode. In 9 × 9-bit mode, there are four adder/subtractor
blocks and two summation blocks.
(2) These signals are either not registered, registered once, or registered twice to match the data path pipeline.
118
Preliminary
Altera Corporation