EP1SGX10C Datasheet, PDF (215/262 Pages) Altera Corporation – StratixGX FPGA Family

Timing Model
Table 94. Stratix Performance (Part 2 of 3) Notes (1), (2)
Resources Used
Performance
TriMatrix
memory
M4K block
TriMatrix
memory
M-RAM
block
Applications
LEs
TriMatrix
Memory
Blocks
DSP
Blocks
-5
Speed
Grade
-6
Speed
Grade
-7
Speed
Grade
Simple dual-port RAM 128 × 36 0
1
bit
0 290.86 255.55 222.27
True dual-port RAM 128 × 18 bit 0
1
FIFO 128 × 36 bit
34
1
Single port
RAM 4K × 144 bit
1
1
Simple dual-port
RAM 4K × 144 bit
0
1
True dual-port
RAM 4K × 144 bit
0
1
0 290.86 255.55 222.27
0 290.86 255.55 222.27
0 255.95 223.06 194.06
0 255.95 233.06 194.06
0 255.95 233.06 194.06
Single port
RAM 8K × 72 bit
Simple dual-port
RAM 8K × 72 bit
0
1
0
1
0 278.94 243.19 211.59
0 255.95 223.06 194.06
True dual-port
RAM 8K × 72 bit
0
1
0 255.95 223.06 194.06
Single port
RAM 16K × 36 bit
Simple dual-port
RAM 16K × 36 bit
0
1
0
1
0 280.66 254.32 221.28
0 269.83 237.69 206.82
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Altera Corporation
215
Preliminary