EP1SGX10C Datasheet, PDF (251/262 Pages) Altera Corporation – StratixGX FPGA Family

High-Speed I/O Specification
Table 146. High-Speed I/O Specifications (Part 2 of 4) Notes (1), (2)
Symbol
Conditions
f_HSDR Device
operation
(LVDS,
LVPECL,
HyperTransport
technology)
J = 10
J=8
J=7
J=4
J=2
J = 1 (LVDS and
LVPECL only)
f_HSDRDPA (LVDS, J=10
LVPECL)
J=8
f_HSCLK (Clock
frequency)
(PCML)
f_HSCLK =
f_HSDR / W
W = 1 to 30
f_HSDR Device
operation
(PCML)
J = 10
J=8
J=7
J=4
J=2
J=1
DPA Run
Length
DPA Jitter
Tolerance_(p-p)
all data rates
DPA Minimum
Eye opening
(p-p)
DPA Receiver
Latency
-5 Speed Grade
Min Typ Max
300
840
300
840
300
840
300
840
100
624
100
462
-6 Speed Grade
Min Typ Max
300
840
300
840
300
840
300
840
100
624
100
462
-7 Speed Grade
Min Typ Max
300
840
300
840
300
840
300
840
100
462
100
462
Unit
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
300
1000 300
300
1000 300
10
400 10
840 300
840 300
400 10
840
840
311
Mbps
Mbps
MHz
300
400 300
300
400 300
300
400 300
300
400 300
100
400 100
100
250 100
6400
0.44
0.56
0.56
5
9
5
400 300
400 300
400 300
400 300
400 100
250 100
6400
0.44
0.56
9
5
311
311
311
311
300
200
6400
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
UI
0.44 UI
UI
9 Number
of
parallel
CLK
cycles
Altera Corporation
251
Preliminary