EP1SGX10C Datasheet, PDF (205/262 Pages) Altera Corporation – StratixGX FPGA Family

Operating Conditions
Tables 72 through 92 provide information about specifications and bus
hold parameters for 1.5-V Stratix GX devices. Notes for Tables 73 through
92 immediately follow Table 92.
Table 72. 3.3-V LVDS I/O Specifications
Symbol
V_CCIO
V_{I D} (1)
V_{I C M} (1)
V_OD
∆V_OD
V_OCM
∆V_OCM
R_L
Parameter
Conditions
Minimum
I/O supply voltage
3.135
Input differential voltage
swing (single-ended)
Input common-mode
voltage
Differential output voltage
Change in V_OD between
high and low
Output common-mode
voltage
Change in V_OCM between
high and low
Receiver differential input
resistor, external
0.1 V < V_{C M} < 1.1 V
W = 1 through 10
1.1 V < V_{C M} < 1.6 V
W=1
1.1 V < V_{C M} < 1.6 V
W = 2 through 10
1.6 V < V_{C M} < 1.8 V
W = 1 through 10
LVDS
0.3 V < V_{I D} < 1.0 V
W = 1 through 10
LVDS
0.3 V < V_{I D} < 1.0 V
W = 1 through 10
LVDS
0.2 V < V_{I D} < 1.0 V
W=1
LVDS
0.1 V < V_{I D} < 1.0 V
W = 2 through 10
R_L = 100 Ω
R_L = 100 Ω
R_L = 100 Ω
R_L = 100 Ω
300
200
100
300
100
1,600
1,100
1,100
250
1,125
90
Typical
3.3
Maximum
3.465
1,000
Units
V
mV
1,000
mV
1,000
mV
1,000
mV
1,100
mV
1,800
mV
1,600
mV
1,600
mV
375
550
mV
50
mV
1,200
1,375
mV
50
mV
100
110
Ω
Note to Table 72:
(1) For up to 1 Gbps in DPA mode and 840 Mbps in non-DPA mode
Altera Corporation
205
Preliminary