EP1SGX10C Datasheet, PDF (229/262 Pages) Altera Corporation – StratixGX FPGA Family

Timing Model
Table 112. Stratix GX Global Clock External I/O Timing Parameters (Part 2 of 2) Notes (1), (2)
Symbol
t_INHPLL
t_OUTCOPLL
Parameter
Conditions
Hold time for input or bidirectional pin using column IOE
input register with global clock fed by enhanced PLL with
default phase setting
Clock-to-output delay output or bidirectional pin using
C_{L O A D} = 10 pF
column IOE output register with global clock enhanced PLL
with default phase setting
Notes to Table 112:
(1) These timing parameters are sample-tested only.
(2) These timing parameters are for column IOE pins. Row IOE pins are 100- to 250-ps slower depending on device,
speed grade, and the specific parameter in question. Designers should use the Quartus II software to verify the
external timing for any pin.
Tables 113 through 118 show the external timing parameters on column
and row pins for EP1SGX10 devices.
Table 113. EP1SGX10 Column Pin Fast Regional Clock External I/O Timing Parameters
Symbol
t_INSU
t_INH
t_OUTCO
-5 Speed Grade
Min
Max
-6 Speed Grade
Min
Max
-7 Speed Grade
Unit
Min
Max
2.245
2.332
2.666
ns
0.000
0.000
0.000
ns
2.000
4.597
2.000
4.920
2.000
5.635
ns
Table 114. EP1SGX10 Column Pin Regional Clock External I/O Timing Parameters
Symbol
t_INSU
t_INH
t_OUTCO
t_INSUPLL
t_INHPLL
t_OUTCOPLL
-5 Speed Grade
Min
Max
-6 Speed Grade
Min
Max
-7 Speed Grade
Unit
Min
Max
2.114
2.218
2.348
ns
0.000
0.000
0.000
ns
2.000
4.728
2.000
5.078
2.000
6.004
ns
1.035
0.941
1.070
ns
0.000
0.000
0.000
ns
0.500
2.629
0.500
2.769
0.500
3.158
ns
Altera Corporation
229
Preliminary