EP1SGX10C Datasheet, PDF (49/262 Pages) Altera Corporation – StratixGX FPGA Family

Source-Synchronous Signaling with DPA
Figure 35. Receiver Timing Diagram
Internal ×1 clock
Internal ×10 clock
RXLOADEN
Receiver
data input
n–1 n–0 9
8
7
6
5
4
3
2
1
0
Stratix GX Differential I/O Transmitter Operation
Designers can configure any of the Stratix GX differential output
channels as a transmitter channel. The differential transmitter is used to
serialize outbound parallel data.
The logic array sends parallel data to the SERDES transmitter circuit
when the TXLOADEN signal is asserted. This signal is generated by the
high-speed counter circuitry of the logic array low-frequency clock’s
rising edge. The data is then transferred from the parallel register into the
serial shift register by the TXLOADEN signal on the third rising edge of the
high-frequency clock.
Figure 36 shows the block diagram of a single SERDES transmitter
channel and Figure 37 shows the timing relationship between the data
and clocks in Stratix GX devices in ×10 mode. W is the low-frequency
multiplier and J is the data parallelization division factor.
Altera Corporation
49
Preliminary