EP1SGX10C Datasheet, PDF (157/262 Pages) Altera Corporation – StratixGX FPGA Family

I/O Structure
I/O Structure
Phase Shifting
Stratix GX device fast PLLs have advanced clock shift capability that
enables programmable phase shifts. Designers can enter a phase shift (in
degrees or time units) for each PLL clock output port or for all outputs
together in one shift. Designers can perform phase shifting in time units
with a resolution range of 150 to 400 ps. This resolution is a function of the
VCO period.
Control Signals
The fast PLL has the same lock output, pllenable input, and areset
input control signals as the enhanced PLL.
For more information on high-speed differential I/O support, see
“Source-Synchronous Signaling with DPA” on page 46.
IOEs provide many features, including:
■ Dedicated differential and single-ended I/O buffers
■ 3.3-V, 64-bit, 66-MHz PCI compliance
■ 3.3-V, 64-bit, 133-MHz PCI-X 1.0 compliance
■ Joint Test Action Group (JTAG) boundary-scan test (BST) support
■ Differential on-chip termination for LVDS I/O standard
■ Programmable pull-up during configuration
■ Output drive strength control
■ Slew-rate control
■ Tri-state buffers
■ Bus-hold circuitry
■ Programmable pull-up resistors
■ Programmable input and output delays
■ Open-drain outputs
■ DQ and DQS I/O pins
■ Double-data rate (DDR) Registers
The IOE in Stratix GX devices contains a bidirectional I/O buffer, six
registers, and a latch for a complete embedded bidirectional single data
rate or DDR transfer. Figure 102 shows the Stratix GX IOE structure. The
IOE contains two input registers (plus a latch), two output registers, and
two output enable registers. The design can use both input registers and
the latch to capture DDR input and both output registers to drive DDR
outputs. Additionally, the design can use the output enable (OE) register
for fast clock-to-output enable timing. The negative edge-clocked OE
register is used for DDR SDRAM interfacing. The Quartus II software
automatically duplicates a single OE register that controls multiple
output or bidirectional pins.
Altera Corporation
157
Preliminary