EP1SGX10C Datasheet, PDF (97/262 Pages) Altera Corporation – StratixGX FPGA Family

TriMatrix Memory
Figure 64. Left-Facing M-RAM to Interconnect Interface Notes (1), (2)
M512 RAM Block Columns
Row Unit Interface
Allows LAB Rows to
Drive Address and
Control Signals to
M-RAM Block
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
LABs in Row
M-RAM Boundary
B1
B2
B3
B4
B5
B6
Port B
LABs in Column
M-RAM Boundary
Column Interface Block
Drives to and from
C4 and C8 Interconnects
M-RAM Block
Port A
A1
A2
A3
A4
A5
A6
Column Interface Block
Allows LAB Columns to
Drive datain and dataout to
and from M-RAM Block
LAB Interface
Blocks
Notes to Figure 64:
(1) Only R24 and C16 interconnects cross the M-RAM block boundaries.
(2) The right-facing M-RAM block has interface blocks on the right side, but none on the left. B1 to B6 and A1 to A6
orientation is clipped across the vertical axis for right-facing M-RAM blocks.
Altera Corporation
97
Preliminary