EP1SGX10C Datasheet, PDF (137/262 Pages) Altera Corporation – StratixGX FPGA Family

PLLs & Clock Networks
Figure 91. EP1SGX40 Device I/O Clock Groups
IO_CLKA[7:0]
IO_CLKB[7:0]
IO_CLKC[7:0]
IO_CLKD[7:0]
8
8
8
8
I/O Clock Regions
8
IO_CLKP[7:0]
8
IO_CLKO[7:0]
13
22 Clocks in the 22 Clocks in the 22 Clocks in the 22 Clocks in the
Half-Quadrant
Half-Quadrant Half-Quadrant
Half-Quadrant
14
8
IO_CLKN[7:0]
8
IO_CLKM[7:0]
17
22 Clocks in the _{22 Clocks in the 22 Clocks in the 22 Clocks in the}
16
Half-Quadrant _{Half-Quadrant Half-Quadrant}
Half-Quadrant
15
8
8
8
8
IO_CLKL[7:0]
IO_CLKK[7:0]
IO_CLKJ[7:0]
IO_CLKI[7:0]
Designers can use the Quartus II software to control whether a clock
input pin is either global, regional, or fast regional. The Quartus II
software automatically selects the clocking resources if not specified.
Enhanced & Fast PLLs
Stratix GX devices provide robust clock management and synthesis using
up to four enhanced PLLs and four fast PLLs. These PLLs increase
performance and provide advanced clock interfacing and clock frequency
synthesis. With features such as clock switchover, spread spectrum
Altera Corporation
137
Preliminary