EP1SGX10C Datasheet, PDF (133/262 Pages) Altera Corporation – StratixGX FPGA Family

PLLs & Clock Networks
Figure 87. EP1SGX25 & EP1SGX10 Device Fast Clock Pin Connections to Fast
Regional Clocks
Fast Clock
Fast Clock
[3..2]
[1..0]
FCLK[1..0]
FCLK[1..0]
FCLK[1..0]
[5..4]
Fast Clock
FCLK[1..0]
[7..6]
Fast Clock
Altera Corporation
133
Preliminary