EP1SGX10C Datasheet, PDF (148/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
External Clock Outputs
Enhanced PLLs 5 and 6 each support up to eight single-ended clock
outputs (or four differential pairs). See Figure 98.
Figure 98. External Clock Outputs for PLLs 5 & 6
From IOE (1)
(2)
e0 Counter
extclk0_a
From IOE (1)
From IOE (1)
extclk0_b
extclk1_a
e1 Counter
4 ^{From IOE (1)}
From IOE (1)
extclk1_b
extclk2_a
e2 Counter
From IOE (1)
From IOE (1)
extclk2_b
extclk3_a
e3 Counter
From IOE (1)
extclk3_b
Notes to Figure 98:
(1) Each external clock output pin can be used as a general purpose output pin from
the logic array. These pins are multiplexed with IOE outputs.
(2) Two single-ended outputs are possible per output counter—either two outputs of
the same frequency and phase or one shifted 180°.
148
Preliminary
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