EP1SGX10C Datasheet, PDF (216/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Table 94. Stratix Performance (Part 3 of 3) Notes (1), (2)
Resources Used
Performance
Applications
TriMatrix
memory
M-RAM
block
True dual-port
RAM 16K × 36 bit
Single port
RAM 32K × 18 bit
Simple dual-port
RAM 32K × 18 bit
True dual-port
RAM 32K × 18 bit
Single port
RAM 64K × 9 bit
Simple dual-port
RAM 64K × 9 bit
DSP block
Larger
Designs
True dual-port
RAM 64K × 9 bit
9 × 9-bit multiplier (3)
18 × 18-bit multiplier (4)
36 × 36-bit multiplier (4)
36 × 36-bit multiplier (5)
18-bit, 4-tap FIR filter
8-bit, 16-tap parallel FIR filter
8-bit, 1,024-point FFT function
LEs
TriMatrix
Memory
Blocks
DSP
Blocks
-5
Speed
Grade
-6
Speed
Grade
-7
Speed
Grade
0
1
0 269.83 237.69 206.82
Units
MHz
0
1
0
1
0 275.86 244.55 212.76 MHz
0 275.86 244.55 212.76 MHz
0
1
0 275.86 244.55 212.76 MHz
0
1
0
1
0 287.85 253.29 220.36 MHz
0 287.85 253.29 220.36 MHz
0
1
0 287.85 253.29 220.36 MHz
0
0
0
0
0
0
0
0
0
0
58
0
870
5
1 335.0 293.94 255.68 MHz
1 278.78 237.41 206.52 MHz
1 148.25 134.71 117.16 MHz
1 278.78 237.41 206.52 MHz
1 278.78 237.41 206.52 MHz
4 141.26 133.49 114.88 MHz
1 261.09 235.51 205.21 MHz
Notes to Table 94:
(1) These design performance numbers were obtained using the Quartus II software.
(2) Numbers not listed will be included in a future version of the data sheet.
(3) This application uses registered inputs and outputs.
(4) This application uses registered multiplier input and output stages within the DSP block.
(5) This application uses registered multiplier input, pipeline, and output stages within the DSP block.
216
Preliminary
Altera Corporation