EP1SGX10C Datasheet, PDF (210/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Table 82. SSTL-2 Class I Specifications (Part 2 of 2)
Symbol
V_OH
V_OL
Parameter
High-level output voltage
Low-level output voltage
Conditions Minimum
I_OH = –8.1 mA
(1)
V_TT + 0.57
I_OL = 8.1 mA (1)
Typical Maximum
V_{T T} – 0.57
Units
V
V
Table 83. SSTL-2 Class II Specifications
Symbol
V_CCIO
V_TT
V_REF
V_IH
V_IL
V_OH
V_OL
Parameter
Output supply voltage
Termination voltage
Reference voltage
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
Conditions Minimum
2.3
V_{R E F} – 0.04
1.15
V_{R E F} + 0.18
–0.3
I_OH = –16.4 mA V_TT + 0.76
(1)
I_OL = 16.4 mA (1)
Typical
2.5
V_{R E F}
1.25
Maximum
2.7
V_{R E F} + 0.04
1.35
V_CCIO + 0.3
V_{R E F} – 0.18
V_{T T} – 0.76
Units
V
V
V
V
V
V
V
Table 84. SSTL-3 Class I Specifications
Symbol
V_CCIO
V_TT
V_REF
V_IH
V_IL
V_OH
V_OL
Parameter
Output supply voltage
Termination voltage
Reference voltage
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
Conditions Minimum Typical
3.0
3.3
V_{R E F} – 0.05 V_{R E F}
1.3
1.5
V_{R E F} + 0.2
–0.3
I_OH = –8 mA (1) V_TT + 0.6
I_OL = 8 mA (1)
Maximum
3.6
V_{R E F} + 0.05
1.7
V_CCIO + 0.3
V_{R E F} – 0.2
V_{T T} – 0.6
Units
V
V
V
V
V
V
V
Table 85. SSTL-3 Class II Specifications (Part 1 of 2)
Symbol
V_CCIO
V_TT
V_REF
V_IH
Parameter
Output supply voltage
Termination voltage
Reference voltage
High-level input voltage
Conditions
Minimum Typical
3.0
3.3
V_{R E F} – 0.05 V_{R E F}
1.3
1.5
V_{R E F} + 0.2
Maximum
3.6
V_{R E F} + 0.05
1.7
V_CCIO + 0.3
Units
V
V
V
V
210
Preliminary
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