EP1SGX10C Datasheet, PDF (161/262 Pages) Altera Corporation – StratixGX FPGA Family

I/O Structure
Stratix GX devices have an I/O interconnect similar to the R4 and C4
interconnect to drive high-fanout signals to and from the I/O blocks.
There are 16 signals that drive into the I/O blocks composed of four
output enables io_boe[3..0], four clock enables io_bce[3..0], four
clocks io_bclk[3..0], and four clear signals io_bclr[3..0]. The
pin’s datain signals can drive the IO interconnect, which in turn drives
the logic array or other I/O blocks. In addition, the control and data
signals can be driven from the logic array, providing a slower but more
flexible routing resource. The row or column IOE clocks, io_clk[7..0],
provide a dedicated routing resource for low-skew, high-speed clocks.
I/O clocks are generated from regional, global, or fast regional clocks (see
“PLLs & Clock Networks” on page 129). Figure 105 illustrates the signal
paths through the I/O block.
Figure 105. Signal Path Through the I/O Block
From I/O
Interconnect
Row or Column
io_clk[7..0]
io_boe[3..0]
io_bce[3..0]
io_bclk[3..0]
io_bclr[3..0]
To Other
IOEs
To Logic
Array
io_datain0
io_datain1
oe
ce_in
io_coe
ce_out
Control
aclr/preset
IOE
io_cce_in
Signal
io_cce_out
Selection
sclr
From Logic
Array
io_cclr
clk_in
io_cclk
clk_out
io_dataout0
io_dataout1
Each IOE contains its own control signal selection for the following
control signals: oe, ce_in, ce_out, aclr/preset, sclr/preset,
clk_in, and clk_out. Figure 106 illustrates the control signal selection.
Altera Corporation
161
Preliminary