EP1SGX10C Datasheet, PDF (121/262 Pages) Altera Corporation – StratixGX FPGA Family

Figure 78. Simple Multiplier Mode
signa (1)
signb (1)
aclr
clock
ena
shiftin B shiftin A
Digital Signal Processing Block
Data A
Data B
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
Data Out
shiftout B shiftout A
Note to Figure 78:
(1) These signals are not registered or registered once to match the data path pipeline.
DSP blocks can also implement one 36 × 36-bit multiplier in multiplier
mode. DSP blocks use four 18 × 18-bit multipliers combined with
dedicated adder and internal shift circuitry to achieve 36-bit
multiplication. The input shift register feature is not available for the
36 × 36-bit multiplier. In 36 × 36-bit mode, the device can use the register
that is normally a multiplier-result-output register as a pipeline stage for
the 36 × 36-bit multiplier. Figure 79 shows the 36 × 36-bit multiply mode.
Altera Corporation
121
Preliminary