EP1SGX10C Datasheet, PDF (221/262 Pages) Altera Corporation – StratixGX FPGA Family

Timing Model
Table 102. Stratix GX Reset & PLL Lock Time Parameter Descriptions
(Part 2 of 2)
Symbol
Parameter
t_{R X _ F R E Q L O C K}
t_{RX_FREQLOCK2PHASELOCK}
The time until the clock recovery unit (CRU) switches to
data mode from lock to reference mode.
The time until CRU phase locks to data after switching
from lock to data mode.
Figure 124 shows the TriMatrix memory waveforms for the M512, M4K,
and M-RAM timing parameters shown in Tables 98 through 100 above.
Figure 124. Dual-Port RAM Timing Microparameter Waveform
wrclock
wren
tWEREH
wraddress
data-in
rdclock
rden
rdaddress
reg_data-out
unreg_data-out
an-1
an
a0
din-1
tDATAH
din
tDATASU
tWERESU
bn
doutn-2
doutn-1
b0
doutn-1
doutn
a1
a2
tWEREH
tRC
b1
tDATACO1
doutn
tDATACO2
dout0
tWERESU
tWADDRSU
a3
tWADDRH
a4
a5
din4
din5
a6
din6
b2
b3
dout0
Altera Corporation
221
Preliminary