EP1SGX10C Datasheet, PDF (247/262 Pages) Altera Corporation – StratixGX FPGA Family

Timing Model
Table 142. Stratix GX Maximum Input Clock Rate for CLK[1, 3, 8, 10] Pins (Part 2 of 2)
I/O Standard
1.8 V
1.5 V
LVCMOS
GTL
GTL+
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
SSTL-18 class I
SSTL-18 class II
1.5-V HSTL class I
1.5-V HSTL class II
1.8-V HSTL class I
1.8-V HSTL class II
3.3-V PCI
3.3-V PCI-X 1.0
Compact PCI
AGP 1×
AGP 2×
CTT
Differential HSTL
LVDS
LVPECL
PCML
HyperTransport technology
-5 Speed Grade -6 Speed Grade -7 Speed Grade
422
422
390
422
422
390
422
422
390
300
250
200
300
250
200
400
350
300
400
350
300
400
350
300
400
350
300
400
350
300
400
350
300
400
350
300
400
350
300
400
350
300
400
350
300
422
422
390
422
422
390
422
422
390
422
422
390
422
422
390
300
250
200
400
350
300
645
645
640
645
645
640
300
275
275
645
645
640
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Tables 143 and 144 show the maximum output clock rate for column and
row pins in Stratix GX devices.
Table 143. Stratix GX Maximum Output Clock Rate for PLL[5, 6, 11, 12] Pins (Part 1 of 2)
LVTTL
2.5 V
I/O Standard
-5 Speed Grade -6 Speed Grade -7 Speed Grade Unit
350
300
250
MHz
350
300
300
MHz
Altera Corporation
247
Preliminary