EP1SGX10C Datasheet, PDF (150/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Table 40. I/O Standards Supported for Enhanced PLL Pins (Part 2 of 2)
I/O Standard
SSTL-2 class I
SSTL-2 class II
SSTL-3 class I
SSTL-3 class II
AGP (1× and 2×)
CTT
INCLK
v
v
v
v
v
v
Input
FBIN
v
v
v
v
v
v
PLLENABLE
Output
EXTCLK
v
v
v
v
v
v
Enhanced PLLs 11 and 12 support one single-ended output each (see
Figure 99). These outputs do not have their own VCC and GND signals.
Therefore, to minimize jitter, do not place switching I/O pins next to this
output pin.
Figure 99. External Clock Outputs for Enhanced PLLs 11 & 12
g0
Counter
CLK13n, I/O, PLL11_OUT
or CLK6n, I/O, PLL12_OUT (1)
From Internal
Logic or IOE
Note to Figure 99:
(1) For PLL 11, this pin is CLK13n; for PLL 12 this pin is CLK7n.
Stratix GX devices can drive any enhanced PLL driven through the global
clock or regional clock network to any general I/O pin as an external
output clock. The jitter on the output clock is not guaranteed for these
cases.
150
Preliminary
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