EP1SGX10C Datasheet, PDF (183/262 Pages) Altera Corporation – StratixGX FPGA Family

IEEE Std. 1149.1 (JTAG) Boundary-Scan Support
IEEE Std. 1149.1
(JTAG)
Boundary-Scan
Support
All Stratix GX devices provide JTAG BST circuitry that complies with the
IEEE Std. 1149.1a-1990 specification. JTAG boundary-scan testing can be
performed either before or after, but not during configuration. Stratix GX
devices can also use the JTAG port for configuration together with either
the Quartus II software or hardware using either Jam Files (.jam) or Jam
Byte-Code Files (.jbc).
Stratix GX devices support IOE I/O standard setting reconfiguration
through the JTAG BST chain. The JTAG chain can update the I/O
standard for all input and output pins any time before or during user
mode. Designers can use this ability for JTAG testing before configuration
when some of the Stratix GX pins drive or receive from other devices on
the board using voltage-referenced standards. Because the Stratix GX
device may not be configured before JTAG testing, the I/O pins may not
be configured for appropriate electrical standards for chip-to-chip
communication. Programming those I/O standards via JTAG allows full
designers to fully test I/O connection to other devices.
The enhanced PLL reconfiguration bits are part of the JTAG chain before
configuration and after power-up. After device configuration, the PLL
reconfiguration bits are not part of the JTAG chain.
Stratix GX devices also use the JTAG port to monitor the logic operation
of the device with the SignalTap^® embedded logic analyzer. Stratix GX
devices support the JTAG instructions shown in Table 54.
Table 54. Stratix GX JTAG Instructions (Part 1 of 2)
JTAG Instruction
Description
SAMPLE/PRELOAD Allows a snapshot of signals at the device pins to be captured and examined during
normal device operation, and permits an initial data pattern to be output at the device pins.
Also used by the SignalTap^® embedded logic analyzer.
EXTEST (1)
Allows the external circuitry and board-level interconnects to be tested by forcing a test
pattern at the output pins and capturing test results at the input pins.
BYPASS
Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data
to pass synchronously through selected devices to adjacent devices during normal device
operation.
USERCODE
IDCODE
HIGHZ (1)
Selects the 32-bit USERCODE register and places it between the TDI and TDO pins,
allowing the USERCODE to be serially shifted out of TDO.
Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE
to be serially shifted out of TDO.
Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data
to pass synchronously through selected devices to adjacent devices during normal device
operation, while tri-stating all of the I/O pins.
Altera Corporation
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Preliminary