EP1SGX10C Datasheet, PDF (260/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
SignalTap logic analysis, and device configuration. See the Design
Software Selector Guide for more details on the Quartus II software
features.
The Quartus II software supports the Windows 2000/NT/98, Sun Solaris,
Linux Red Hat v6.2 and HP-UX operating systems. It also supports
seamless integration with industry-leading EDA tools through the
NativeLink^® interface.
Device Pin-Outs Device pin-outs for Stratix GX devices will be released on the Altera web
site (www.altera.com).
Ordering
Information
Ordering information will be available in a future version of this data
sheet.
Revision History The information contained in the Stratix GX FPGA Family data sheet
version 2.2 supersedes information published in previous versions.
Version 2.2
The following changes were made to the Stratix GX FPGA Family data
sheet version 2.2:
■ Updated Figures 37, 38, and 125.
■ Updated Tables 61, 66, 102, 109, 140, 141, and 143.
■ Updated the section “Phase Compensation FIFO Buffer” on page 31.
■ Updated the section “Logic Array Blocks” on page 61.
■ Updated the section “Clock Switchover” on page 144.
■ Updated the section “Lock Detect” on page 152.
■ Updated the section “Advanced Clear & Enable Control” on
page 153.
■ Updated the section “I/O Structure” on page 157.
■ Updated the section “Power Sequencing & Hot Socketing” on
page 182.
■ Removed Txz, Tzx, Tzxpll, and Txzpll parameters because of errors
in data. These parameters will be added in when new data is
available.
Version 2.1
The following changes were made to the Stratix GX FPGA Family data
sheet version 2.1:
260
Preliminary
Altera Corporation