EP1SGX10C Datasheet, PDF (140/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Figure 92. PLL Floorplan
FPLL7CLK 7
CLK[15..12]
5 11
High-Speed
Transceivers
inclk1
1
CLK[3..0]
2
PLLs
FPLL8CLK 8
inclk2
inclk3
inclk4
inclk5
6 12
CLK[7..4]
Figure 93 shows the global and regional clock connections from the PLL
outputs and the CLK pins.
140
Preliminary
Altera Corporation