EP1SGX10C Datasheet, PDF (222/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Figure 125. Stratix GX Transceiver Reset & PLL Lock Time Waveform Note (1)
Reset Signals
pll_areset
T_{analogresetPW}
rx_analogreset
tx_digitalreset
T_{digitalresetPW}
rx_digitalreset
Output Status Signals
pll_locked
rx_freqlocked
Ttx_pll_lock
Trx_freqlock
Trx_freqlock2phaselock
CRU Phase
Locked to Data
Note to Figure 125:
(1) Waveforms are for minimum pulse width timing and output timing only. Please refer to the Stratix GX User’s Guide
for the complete reset sequence.
Tables 103 through 109 show the internal timing microparameters for all
Stratix GX devices.
Table 103. LE Internal Timing Microparameters
Symbol
t_SU
t_H
t_CO
t_LUT
t_CLR
t_PRE
t_CLKHL
-5 Speed Grade -6 Speed Grade -7 Speed Grade
Unit
Min Max Min Max Min Max
10
10
11
ns
100
100
114
ns
156
176
202
ns
366
459
527
ns
100
100
114
ns
100
100
114
ns
100
100
114
ns
222
Preliminary
Altera Corporation