EP1SGX10C Datasheet, PDF (171/262 Pages) Altera Corporation – StratixGX FPGA Family

Figure 112. Simplified Diagram of the DQS Phase-Shift Circuitry
Input
Reference
Clock
Phase
Comparator
Up/Down
Counter
I/O Structure
Delay Chains
6
Control Signals
to DQS Pins
See the External Memory Interfaces chapter in the Stratix Device Handbook,
Volume 2 for more information on external memory interfaces.
Programmable Drive Strength
The output buffer for each Stratix GX device I/O pin has a programmable
drive strength control for certain I/O standards. The LVTTL and
LVCMOS standard has several levels of drive strength that the user can
control. SSTL-3 class I and II, SSTL-2 class I and II, HSTL class I and II, and
3.3-V GTL+ support a minimum setting, the lowest drive strength that
guarantees the I_OH/I_OL of the standard. Using minimum settings
provides signal slew rate control to reduce system noise and signal
overshoot.
Altera Corporation
171
Preliminary