EP1SGX10C Datasheet, PDF (200/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Table 66. Stratix GX Transceiver Block AC Specification (Part 2 of 3)
-6 Commercial &
-7 Commercial &
-5 Commercial
Industrial Speed
Industrial Speed
Symbol /
Description
Conditions
Speed Grade (5)
Grade
(5)
Grade
Unit
(5)
Min Typ Max Min Typ Max Min Typ Max
Receive
sinusoidal
jitter
tolerance
(peak-to-
peak)
BER
Receive
latency (2)
f = 22.1 Khz
@
3.125 Gbps
f = 1.875 MHz
@
3.125 Gbps
f = 20 MHz @
3.125 Gbps
Single width 7
Double width 5
Channel to
channel bit
skew
tolerance (4),
(7)
XAUI mode /
inter quadrant
only
Run-length
8.5
0.1
0.1
10^-12
32
7
19
5
40
80
8.5
0.1
0.1
10^-12
32
7
19
5
40
80
N/A
UI
N/A
UI
N/A
UI
10^-12
32
19
40
Number
of parallel
clocks
Number
of parallel
clocks
UI
80
UI
Receiver
100 MHz to
–10
return loss 2.5 Ghz
(differential)
Receiver
100 MHz to
–6
return loss 2.5 Ghz
(common
mode)
–10
–10
dB
–6
–6
dB
Transmitter
Serial data
rate
Commercial / 500
industrial
Parallel
20
transceiver/
core interface
speed
Serial data
output
deterministic
jitter
TDJ @
3.125 Gbps
Serial data
output total
jitter
TTJ @
3.125 Gbps
3,187.5 500
398.4 20
±0.07
±0.175
3,187.5 500
375 20
2500
312.5
Mbps
MHz
±0.07 N/A N/A N/A
UI
±0.175 N/A N/A N/A
UI
200
Preliminary
Altera Corporation