EP1SGX10C Datasheet, PDF (255/262 Pages) Altera Corporation – StratixGX FPGA Family

High-Speed I/O Specification
Table 147. Enhanced PLL Specifications for -5 Speed Grades (Part 2 of 2)
Symbol
Parameter
Min Typ
Max
Unit
% spread Percentage spread for spread
0.4 0.5
0.6
%
spectrum frequency (9)
t_ARESET
Minimum pulse width on areset
10
ns
signal
Table 148. Enhanced PLL Specifications for -6 Speed Grades (Part 1 of 2)
Symbol
f_IN
f_INDUTY
f_EINDUTY
t_INJITTER
t_EINJITTER
t_FCOMP
f_OUT
f_{OUT_EXT}
t_OUTDUTY
t_JITTER
t_CONFIG5,6
t_CONFIG11,12
t_SCANCLK
t_DLOCK
t_LOCK
f_VCO
t_LSKEW
Parameter
Min Typ
Input clock frequency
3 (1)
Input clock duty cycle
40
External feedback clock input duty
40
cycle
Input clock period jitter
External feedback clock period jitter
External feedback clock compensation
time (3)
Output frequency for internal global or 0.3
regional clock
Output frequency for external clock (2) 0.3
Duty cycle for external clock output
45
(when set to 50%)
Period jitter for external clock output (5)
Time required to reconfigure the scan
chains for PLLs 5 and 6
Time required to reconfigure the scan
chains for PLLs 11 and 12
scanclk frequency (4)
Time required to lock dynamically (after (8)
switchover or reconfiguring any non-
post-scale counters/delays) (6) (10)
Time required to lock from end of
10
device configuration (10)
PLL internal VCO operating range
300
Clock skew between two external clock
±50
outputs driven by the same counter
Max
650
60
60
±200 (2)
±200 (2)
6
450
500
55
±100 ps for >200 MHz outclk
±20 mUI for <200 MHz outclk
289/f_SCANCLK
193/f_SCANCLK
22
100
400
800 (7)
Unit
MHz
%
%
ps
ps
ns
MHz
MHz
%
ps or
mUI
MHz
µs
µs
MHz
ps
Altera Corporation
255
Preliminary