EP1SGX10C Datasheet, PDF (41/262 Pages) Altera Corporation – StratixGX FPGA Family

Transceiver Blocks
Figure 32. EP1SGX40 Receiver PLL Recovered Clock to Regional Clock
Connection
Stratix GX
PLD
Transceiver Blocks
Block 0
RCLK[11..10]
Block 1
Block 4
Block 2
RCLK[9..8]
Block 3
Figure 33 shows the possible recovered clock connection to the fast
regional clock resource. The fast regional clocks can drive logic in their
associated regions.
Altera Corporation
41
Preliminary