EP1SGX10C Datasheet, PDF (37/262 Pages) Altera Corporation – StratixGX FPGA Family

Transceiver Blocks
Figure 28. EP1SGX25F Device Inter-Transceiver & Global Clock Connections Note (1)
IQ0 IQ1 IQ2
Transceiver Block 0
Global Clocks,
I/O Bus,
General Routing
IQ0
IQ1
refclkb
/2
IQ2
Global Clocks,
I/O Bus,
General Routing
Transmitter
PLL
4
Receiver
PLLs (2)
Global Clocks,
I/O Bus,
General Routing
Global Clocks,
I/O Bus,
General Routing
Transceiver Block 1
IQ0
IQ1
refclkb
/2
IQ2
Global Clocks,
I/O Bus,
General Routing
Global Clocks,
I/O Bus,
General Routing
Transceiver Block 2
IQ0
IQ1
refclkb
/2
IQ2
Global Clocks,
I/O Bus,
General Routing
Global Clocks,
I/O Bus,
General Routing
Transceiver Block 3
IQ0
IQ1
refclkb
/2
IQ2
Transmitter
PLL
4
Receiver
PLLs (2)
Transmitter
PLL
4
Receiver
PLLs (2)
Transmitter
PLL
4
Receiver
PLLs (2)
PLD
Global
Clocks
16
Notes to Figure 28:
(1) IQ lines are inter-transceiver block lines.
(2) There are four receiver PLLs in each transceiver block.
Altera Corporation
37
Preliminary