EP1SGX10C Datasheet, PDF (243/262 Pages) Altera Corporation – StratixGX FPGA Family

Timing Model
Table 138. Stratix GX IOE Programmable Delays on Row Pins
Parameter
Setting
Decrease input delay to Off
internal cells
On
Small
Medium
Large
Decrease input delay to Off
input register
On
Decrease input delay to Off
output register
On
Increase delay to output Off
pin
On
Increase delay to output Off
enable pin
On
Increase output clock
Off
enable delay
On
Small
Large
Increase input clock enable Off
delay
On
Small
Large
Increase output enable Off
clock enable delay
On
Small
Large
-5 Speed Grade
Min Max
3,970
3,390
2,810
164
164
3,900
0
1,240
0
0
377
0
348
0
180
260
260
0
180
260
260
0
540
1,016
1,016
-6 Speed Grade
Min Max
4,367
3,729
3,091
173
173
4,290
0
1,364
0
0
397
0
383
0
198
286
286
0
198
286
286
0
594
1,118
1,118
-7 Speed Grade
Unit
Min Max
5,022 ps
4,288 ps
3,554 ps
198
ps
198
ps
4,933 ps
0
ps
1,568 ps
0
ps
0
ps
456
ps
0
ps
441
ps
0
ps
227
ps
328
ps
328
ps
0
ps
227
ps
328
ps
328
ps
0
ps
683
ps
1,285 ps
1,285 ps
Altera Corporation
243
Preliminary