EP1SGX10C Datasheet, PDF (253/262 Pages) Altera Corporation – StratixGX FPGA Family

High-Speed I/O Specification
Table 146. High-Speed I/O Specifications (Part 4 of 4) Notes (1), (2)
Symbol
Conditions
-5 Speed Grade -6 Speed Grade -7 Speed Grade
Unit
Min Typ Max Min Typ Max Min Typ Max
Output jitter
All
(peak-to-peak)
160
160
200 ps
Output t_RISE
LVDS
HyperTransport
technology
80 110 120 80 110 120 80 110 120 ps
110 170 200 110 170 200 120 170 200 ps
LVPECL
90 130 150 90 130 150 100 135 150 ps
PCML
80 110 135 80 110 135 80 110 135 ps
Output t_FALL
LVDS
HyperTransport
technology
80 110 120 80 110 120 80 110 120 ps
110 170 200 110 170 200 110 170 200 ps
LVPECL
90 130 160 90 130 160 100 135 160 ps
PCML
105 140 175 105 140 175 110 145 175 ps
t_DUTY
LVDS (J = 2 through 47.5 50 52.5 47.5 50 52.5 47.5 50 52.5 %
10)
LVDS (J =1) and
LVPECL, PCML,
HyperTransport
technology
45 50 55 45 50 55 45 50 55
%
t_LOCK
All
100
100
100 µs
Notes to Table 146:
(1) When J = 4, 7, 8, and 10, the SERDES block is used.
(2) When J = 2 or J = 1, the SERDES is bypassed.
Altera Corporation
253
Preliminary