EP1SGX10C Datasheet, PDF (132/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Figure 86. Regional Clocks
RCLK[15..14] RCLK[13..12]
CLK[15..12]
RCLK[1..0]
CLK[3..0]
RCLK[3..2]
RCLK[11..10]
Transceiver
Clocks
RCLK[9..8]
CLK[7..4]
RCLK[5..4]
RCLK[7..6]
Regional Clocks Only Drive a Device
Quadrant from Specified CLK Pins,
Recovered Clocks, or PLLs within
that Quadrant
Fast Regional Clock Network
In EP1SGX25 and EP1SGX10 devices, there are two fast regional clock
networks, FCLK[1..0], within each quadrant, fed by input pins (see
Figure 87). In EP1SGX40 devices, there are two fast regional clock
networks within each half-quadrant (see Figure 88). The FCLK[1..0]
clocks can also be used for high fanout control signals, such as
asynchronous clears, presets, clock enables, or protocol control signals
such as TRDY and IRDY for PCI. Dual-purpose FCLK pins drive the fast
clock networks. All devices have eight FCLK pins to drive fast regional
clock networks. Any I/O pin can drive a clock or control signal onto any
fast regional clock network with the addition of a delay. The I/O
interconnect drives this signal.
132
Preliminary
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