EP1SGX10C Datasheet, PDF (167/262 Pages) Altera Corporation – StratixGX FPGA Family

I/O Structure
Figure 110. Stratix GX IOE in DDR Output I/O Configuration Notes (1), (2)
Column or Row
Interconnect
IOE_CLK[7..0]
I/O Interconnect
[15..0]
clkout
aclr/prn
Output
Enable Clock
Enable Delay
Output Clock
Enable Delay
Chip-Wide Reset
sclr
OE Register
D
Q
ENA
CLRN/PRN
Output
t_ZX Delay
OE Register
t_CO Delay
OE Register
D
Q
ENA
CLRN/PRN
Used for
DDR SDRAM
V_CCIO
Optional
PCI Clamp
V_CCIO
Programmable
Pull-Up
Resistor
Logic Array
to Output
Register Delay
Logic Array
to Output
Register Delay
Output Register
D
Q
ENA
CLRN/PRN
Output Register
D
Q
Output
Pin Delay
clk
Drive Strength Control
Open-Drain Output
Slew Control
ENA
CLRN/PRN
Bus-Hold
Circuit
Notes to Figure 110:
(1) All input signals to the IOE can be inverted at the IOE.
(2) The tristate is by default active high. It can, however, be designed to be active low.
Altera Corporation
167
Preliminary