EP1SGX10C Datasheet, PDF (146/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
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when clock sources can originate from multiple cards on the
backplane, requiring a system-controlled switchover between
frequencies of operation. Designers can use clkswitch together
with the lock signal to trigger the switch from a clock that is running
but becomes unstable and cannot be locked onto.
During switchover, the PLL VCO continues to run and will either slow
down or speed up, generating frequency drift on the PLL outputs. The
clock switchover transitions without any glitches. After the switch, there
is a finite resynchronization period to lock onto new clock as the VCO
ramps up. The exact amount of time it takes for the PLL to relock relates
to the PLL configuration and may be adjusted by using the
programmable bandwidth feature of the PLL. The preliminary
specification for the maximum time to relock is 100 µs.
For more information on clock switchover, see AN313: Implementing
Clock Switchover in Stratix & Stratix GX Devices.
PLL Reconfiguration
The PLL reconfiguration feature enables system logic to change
Stratix GX device enhanced PLL counters and delay elements without
reloading a Programmer Object File (.pof). This provides considerable
flexibility for frequency synthesis, allowing real-time PLL frequency and
output clock delay variation. The designer can sweep the PLL output
frequencies and clock delay in prototype environments. The PLL
reconfiguration feature can also dynamically or intelligently control
system clock speeds or t_CO delays in end systems.
Clock delay elements at each PLL output port implement variable delay.
Figure 97 shows a diagram of the overall dynamic PLL control feature for
the counters and the clock delay elements. The configuration time is less
than 20 µs for the enhanced PLL using a input shift clock rate of 25 MHz.
The charge pump, loop filter components, and phase shifting using VCO
phase taps cannot be dynamically adjusted.
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Preliminary
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