EP1SGX10C Datasheet, PDF (198/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Table 64. Stratix GX Transceiver Block Operating Conditions (Part 2 of 2)
Symbol
V_{O C M}
R_{R E F} (11)
Parameter
Transmitter output common
mode voltage
Reference resistor
Conditions
Commercial
and industrial
Commercial
and industrial
Minimum
2K –1%
Typical Maximum Units
750
mV
2K
2K +1%
Ω
Table 65. Stratix GX Transceiver Block On-Chip Termination
Symbol
Parameter
Conditions
Min Typ Max Units
Rx
Receiver termination Commercial and industrial, 100-Ω setting 103 108 113 Ω
Commercial and industrial, 120-Ω setting 120 128 134 Ω
Commercial and industrial, 150-Ω setting 149 158 167 Ω
Tx
Transmitter termination Commercial and industrial, 100-Ω setting 103 108 113 Ω
Commercial and industrial, 120-Ω setting 120 128 134 Ω
Commercial and industrial, 150-Ω setting 149 158 167 Ω
Refclkb Dedicated transceiver Commercial and industrial, 100-Ω setting 103 108 113 Ω
clock termination
Commercial and industrial, 120-Ω setting 120 128 134 Ω
Commercial and industrial, 150-Ω setting 149 158 167 Ω
Notes to Tables 60 through 65:
(1) See the Operating Requirements for Altera Devices Data Sheet.
(2) Conditions beyond those listed in Table 60 may cause permanent damage to a device. Additionally, device
operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device.
(3) Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –0.5 V or overshoot to 4.6 V for
input currents less than 100 mA and periods shorter than 20 ns. (The information in this note does not include the
transceiver pins. See note 13 for information about the transient voltage on the transceiver pins.)
(4) Maximum V_CC rise time is 100 ms, and V_CC must rise monotonically.
(5) V_CCIO maximum and minimum conditions for LVPECL, LVDS, and 3.3-V PCML are shown in parentheses.
(6) All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before V_CCINT and V_CCIO are
powered.
(7) Typical values are for T_A = 25° C, V_CCINT = 1.5 V, and V_CCIO = 1.5 V, 1.8 V, 2.5 V, and 3.3 V.
(8) This value is specified for normal device operation. The value may vary during power-up. This applies for all V_CCIO
settings (3.3, 2.5, 1.8, and 1.5 V).
(9) Pin pull-up resistance values will lower if an external source drives the pin higher than V_CCIO.
(10) The device can tolerate prolonged operation at this absolute maximum, as long as the maximum specification is
not violated.
(11) The DC signal on this pin must be as clean as possible. Ensure that no noise is coupled to this pin.
(12) The Stratix GX device’s recommended operating conditions do not include the transceiver. Refer to Tables 63 to 66.
(13) Minimum DC input to the transceiver pins is –0.5 V. During transitions, the transceiver pins may undershoot to
–0.5 V or overshoot to 3.5 V for input currents less than 100 mA and periods shorter than 20 ns.
198
Preliminary
Altera Corporation