EP1SGX10C Datasheet, PDF (174/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
The bus-hold circuitry uses a resistor with a nominal resistance (R_BH) of
approximately 7 kΩ to weakly pull the signal level to the last-driven state.
Table 4–32 on page 15 gives the specific sustaining current driven
through this resistor and overdrive current used to identify the next-
driven input level. This information is provided for each V_CCIO voltage
level.
The bus-hold circuitry is active only after configuration. When going into
user mode, the bus-hold circuit captures the value on the pin present at
the end of configuration.
Programmable Pull-Up Resistor
Each Stratix GX device I/O pin provides an optional programmable pull-
up resistor during user mode. If this feature is enabled for an I/O pin, the
pull-up resistor (typically 25 kΩ) weakly holds the output to the V_CCIO
level of the output pin’s bank. Table 47 shows which pin types support
the weak pull-up resistor feature.
Table 47. Programmable Weak Pull-Up Resistor Support
I/O pins
Pin Type
CLK[15..0]
FCLK
FPLL[7..10]CLK
Configuration pins
JTAG pins
Programmable Weak Pull-Up Resistor
v
v
v (1)
Note to Table 47:
(1) TDO pins do not support programmable weak pull-up resistors.
Advanced I/O Standard Support
Stratix GX device IOEs support the following I/O standards:
■ LVTTL
■ LVCMOS
■ 1.5 V
■ 1.8 V
■ 2.5 V
■ 3.3-V PCI
■ 3.3-V PCI-X 1.0
■ 3.3-V AGP (1× and 2×)
174
Preliminary
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