EP1SGX10C Datasheet, PDF (51/262 Pages) Altera Corporation – StratixGX FPGA Family

Source-Synchronous Signaling with DPA
The dynamic phase aligner uses both the source clock and the serial data.
The dynamic phase aligner automatically and continuously tracks
fluctuations caused by system variations and self-adjusts to eliminate the
phase skew between the multiplied clock and the serial data. Figure 38
shows the relationship between Stratix GX source-synchronous circuitry
and the Stratix GX source-synchronous circuitry with DPA.
Figure 38. Source-Synchronous DPA Circuitry
Receiver Circuit
rx_in+
rx_in-
Deserializer
(1)
rx_inclock_p
rx_inclock_n
8
×W
PLL
Dynamic
Phase
Aligner
Deserializer (1)
×1
Stratix GX
Logic
Array
Note to Figure 38:
(1) Both deserializers are identical. The deserializer operation is described in the “Principles of SERDES Operation”
section.
Unlike the de-skew function in APEX^TM 20KE and APEX 20KC devices,
designers do not have to use a fixed training pattern with DPA in
Stratix GX devices. Table 18 shows the differences between
source-synchronous circuitry with DPA and source-synchronous
circuitry without DPA circuitry in Stratix GX devices.
Table 18. Source-Synchronous Circuitry With & Without DPA (Part 1 of 2)
Feature
Data rate
Deserialization factors
Clock frequency
Source-Synchronous Circuitry
Without DPA
With DPA
300 to 840 Megabits per 300 Mbps to 1 Gbps
second (Mbps)
1, 2, 4, 8, 10
8, 10
10 to 717 MHz
74 to 717 MHz
Altera Corporation
51
Preliminary