EP1SGX10C Datasheet, PDF (46/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
High-Speed Serial Bus Protocols
With wide, serial data rate range, Stratix GX devices can support
multiple, high-speed serial bus protocols. Table 17 shows some of the
protocols that Stratix GX devices can support.
Table 17. High-Speed Serial Bus Protocols
Bus Transfer Protocol
SONET backplane
10 Gigabit Ethernet XAUI
10 Gigabit fibre channel
InfiniBand
Fibre channel (1G, 2G)
Serial RapidIO^™
PCI Express
SMPTE 292M
Stratix GX (Gbps)
(Supports up to 3.1875 Gbps)
2.488
3.125
3.1875
2.5
1.0625, 2.125
1.25, 2.5, 3.125
2.5
1.485
Source-
Synchronous
Signaling with
DPA
Expansion in the telecommunications market and growth in Internet use
requires systems to move more data faster than ever. To meet this
demand, system designers rely on solutions such as differential signaling
and emerging high-speed interface standards including RapidIO,
POS-PHY 4, SFI-4, or XSBI.
These new protocols support differential data rates up to 1 Gbps and
higher. At these high data rates, it becomes more challenging to manage
the skew between the clock and data signals. One solution to this
challenge is to use CDR to eliminate skew between data channels and
clock signals. Another potential solution, DPA, is beginning to be
incorporated into some of these protocols.
The source-synchronous high-speed interface in Stratix GX devices is a
dedicated circuit embedded into the PLD allowing for high-speed
communications. The High-Speed Differential I/O Interfaces in Stratix
Devices chapter of the Stratix Handbook, Volume 2 provides information on
the high-speed I/O standard features and functions of the Stratix GX
device.
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Preliminary
Altera Corporation