EP1SGX10C Datasheet, PDF (117/262 Pages) Altera Corporation – StratixGX FPGA Family

Digital Signal Processing Block
Pipeline/Post Multiply Register
The output of 9 × 9- or 18 × 18-bit multipliers can optionally feed a register
to pipeline multiply-accumulate and multiply-add/subtract functions.
For 36 × 36-bit multipliers, this register will pipeline the multiplier
function.
Adder/Output Blocks
The result of the multiplier sub-blocks are sent to the adder/output block
which consist of an adder/subtractor/accumulator unit, summation unit,
output select multiplexer, and output registers. The results are used to
configure the adder/output block as a pure output, accumulator, a simple
two-multiplier adder, four-multiplier adder, or final stage of the 36-bit
multiplier. The designer can configure the adder/output block to use
output registers in any mode, and must use output registers for the
accumulator. The system cannot use adder/output blocks independently
of the multiplier. Figure 77 shows the adder and output stages.
Altera Corporation
117
Preliminary