EP1SGX10C Datasheet, PDF (48/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
The data in the serial shift register is shifted into a parallel register by the
RXLOADEN signal generated by the fast PLL counter circuitry on the third
falling edge of the high-frequency clock. However, designers can select
which falling edge of the high frequency clock loads the data into the
parallel register, using the data-realignment circuit.
In normal mode, the enable signal RXLOADEN loads the parallel data into
the next parallel register on the second rising edge of the low-frequency
clock. Designers can also load data to the parallel register through the
TXLOADEN signal when using the data-realignment circuit.
Figure 34 shows the block diagram of a single SERDES receiver channel.
Figure 35 shows the timing relationship between the data and clocks in
Stratix GX devices in ×10 mode. W is the low-frequency multiplier and J
is the data parallelization division factor.
Figure 34. Stratix GX High-Speed Interface Deserialized in ×10 Mode
RXIN+
RXIN−
Receiver Circuit
Serial Shift
Registers
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
Parallel
Registers
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
Parallel
Registers
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
Stratix GX
Logic Array
RXCLKIN+
RXCLKIN−
×W
Fast _RXLOADEN
PLL (2)
TXLOADEN
×W/J (1)
Notes to Figure 34:
(1) W = 1, 2, 4, 7, 8, or 10.
J = 4, 7, 8, or 10 for non-DPA (J = 8 or 10 for DPA).
W does not have to equal J. When J = 1 or 2, the deserializer is bypassed. When J = 2, the device uses DDRIO registers.
(2) This figure does not show additional circuitry for clock or data manipulation.
48
Preliminary
Altera Corporation