EP1SGX10C Datasheet, PDF (33/262 Pages) Altera Corporation – StratixGX FPGA Family

Transceiver Blocks
Parallel Loopback
The parallel loopback mode exercises the digital logic portion of the
transceiver data path. The analog portions are not use in the loopback
path. The received data is not retimed. Figure 24 shows the data path in
parallel loopback mode. This option is not dynamically switchable.
Reception of an external signal is not possible in this mode.
Figure 24. Data Path in Parallel Loopback Mode
BIST PRBS
Verifier
Deserializer
Word
Aligner
Clock
Recovery
Unit
Channel
Aligner
Rate
Matcher
8B/10B
Decoder
Byte
Deserializer
BIST
Incremental
Verifier
Phase
Compensation
FIFO
Serializer
Active Path
Non-active Path
8B/10B
Encoder
BIST PRBS
Generator
Byte
Serializer
Phase
Compensation
FIFO
BIST
Generator
Reverse Serial Loopback
The reverse serial loopback exercises the analog portion of the
transceiver. This loopback mode is dynamically switchable through the
tx_srlpbk port on a channel by channel basis. Asserting
rxanalogreset in reverse serial loopback mode powers down the
receiver buffer and CRU, preventing data loopback. Figure 25 shows the
data path in reverse serial loopback mode.
Altera Corporation
33
Preliminary