EP1SGX10C Datasheet, PDF (160/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Figure 104. Column I/O Block Connection to the Interconnect
42 Data &
Control Signals
from Logic Array (2)
Vertical I/O Block
16 Control
Signals from I/O
Interconnect (1)
I/O Block
Local Interconnect
16
42
IO_datain[3:0]
Vertical I/O
Block Contains
up to Six IOEs
io_clk[7..0]
I/O Interconnect
R4, R8 & R24
Interconnects
LAB
LAB
LAB
LAB Local
Interconnect
C4, C8 & C16
Interconnects
Notes to Figure 104:
(1) The 16 control signals are composed of four output enables io_boe[3..0], four clock enables io_bce[3..0],
four clocks io_bclk[3..0], and four clear signals io_bclr[3..0].
(2) The 42 data and control signals consist of 12 data out lines; six lines each for DDR applications
io_dataouta[5..0] and io_dataoutb[5..0], six output enables io_coe[5..0], six input clock enables
io_cce_in[5..0], six output clock enables io_cce_out[5..0], six clocks io_cclk[5..0], and six clear
signals io_cclr[5..0].
160
Preliminary
Altera Corporation