EP1SGX10C Datasheet, PDF (164/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Programmable delays can increase the register-to-pin delays for output
and/or output enable registers. A programmable delay exists to increase
the t_ZX delay to the output pin, which is required for ZBT interfaces.
Table 42 shows the programmable delays for Stratix GX devices.
Table 42. Stratix GX Programmable Delay Chain
Programmable Delays
Quartus II Logic Option
Input pin to logic array delay
Input pin to input register delay
Decrease input delay to internal cells
Decrease input delay to input register
Output pin delay
Output enable register t_CO delay
Output t_ZX delay
Output clock enable delay
Input clock enable delay
Logic array to output register delay
Output enable clock enable delay
Increase delay to output pin
Increase delay to output enable pin
Increase t_ZX delay to output pin
Increase output clock enable delay
Increase input clock enable delay
Decrease input delay to output register
Increase output enable clock enable delay
The IOE registers in Stratix GX devices share the same source for clear or
preset. The designer can program preset or clear for each individual IOE.
The designer can also program the registers to power up high or low after
configuration is complete. If programmed to power up low, an
asynchronous clear can control the registers. If programmed to power up
high, an asynchronous preset can control the registers. This feature
prevents the inadvertent activation of another device’s active-low input
upon power-up. If one register in an IOE uses a preset or clear signal then
all registers in the IOE must use that same signal if they require preset or
clear. Additionally a synchronous reset signal is available to the designer
for the IOE registers.
Double-Data Rate I/O Pins
Stratix GX devices have six registers in the IOE, which support DDR
interfacing by clocking data on both positive and negative clock edges.
The IOEs in Stratix GX devices support DDR inputs, DDR outputs, and
bidirectional DDR modes.
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Preliminary
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